Design Scheme of PLC Backplane Bus Protocol Interface Chip Based on CPLD

A set of PLC backplane bus protocol interface chip based on CPLD is designed. The protocol chip can distinguish the periodic data and non-periodic data of the backplane bus of PLC. The process of designing state machine, protocol frame controller and FIFO controller through Verilog HDL language is introduced in detail. The test results of stable backplane bus operation at 25MHz verify the feasibility of protocol chip design.

The programmable logic controller (PLC) host supports the expansion module connection through the backplane bus. The backplane bus is a high-speed data path between the PLC host and the I/O expansion module, supporting I/O between the host and the expansion module. The data is refreshed. The technical level of the backplane bus determines the I/O expansion capability of the PLC product and is the core technology of PLC design and manufacturing. At present, PLC mostly uses serial communication technology to realize the backplane bus. The serial bus has few lead wires and low hardware cost. Compared with the parallel bus, it is not easily interfered. The serial bus can improve the automation equipment in harsh factory and industrial environments. reliability. Optional types for serial communication technologies include I2C, UART, SPI, USB, and Ethernet. In general, many of the peripheral components that are the main chip of the PLC integrate themselves. However, the I2C, UART, and SPI peripherals integrated in the microcontroller are too slow to meet the communication speed requirements of the backplane bus. The communication speed of USB and Ethernet is very fast, but since they are all common interfaces, the intervention of the MCU is required when the communication protocol is processed. The data processing speed of the MCU is slow, so the overall communication speed is still very slow. A large PLC typically collects thousands of I/O data for less than 1 ms. To meet such high-speed communication requirements, a dedicated backplane bus must be designed.

1 Backplane bus working principle

As shown in Figure 1, the data communication process based on the backplane bus is as follows:

(1) The command of the PLC host is sent to the backplane bus through the host protocol chip; (2) the slave protocol chip sends the received command to the MCU of the expansion module, and the MCU of one of the expansion modules responds, and the slave protocol chip is passed. Send the response data to the backplane bus; (3) The host protocol chip receives the response data and sends it to the microcontroller of the PLC host.

Figure 1 Backplane bus communication block diagram

The data sent by the PLC host to the backplane bus can be divided into two categories: one is I/O refresh data, which has periodicity, and the data exchange is very frequent; the other is diagnostic data, which has non-periodicity and less chance of occurrence.

2 protocol chip design

This design defines the backplane bus using SPI serial communication specifications. There are 4 leads for communication, including clock signal SCLK, chip select signal SSEL, write data lead MISO and read data lead MOSI. Support both master and slave simultaneously. Transceiver data, the data bit format is shown in Figure 2. The data frame is transmitted when the SSEL signal is low.

Figure 2 Backplane Bus Data Specifications

The internal block diagram of the master and slave protocol chips is the same, as shown in Figure 3.

The protocol chip has a state machine controller, a frame controller, a shift register, a receive/transmit FIFO, and a read/write buffer. The periodic and aperiodic data frames sent by the MCU are first written to the write buffer and queued for transmission in the transmit FIFO. The data frame is converted to serial data and sent to the backplane bus driven by the SPI clock SCLK; Under the action of the clock, receiving serial data from the backplane bus; under the coordination of the state machine and the frame controller, the valid data frame in the receive FIFO is extracted and placed in the read buffer area, waiting for the microcontroller to read, if If the data is non-periodic, an interrupt signal is sent to the microcontroller to retrieve the data. The periodic data in the read buffer can be overwritten, and the newly received periodic data directly overwrites the old periodic data. The non-periodic data is stored separately, cannot be overwritten, and is read and cleared by the single chip microcomputer.

Figure 3 internal block diagram of the protocol chip

The protocol chip enables the external MCU to access the read buffer and the write buffer in an idle state. The MCU does not have to frequently process the periodic data through the interrupt technology, and also allows the PLC host to access the periodic data of the slave without waiting.

3 CPLD-based protocol chip implementation

3.1 CPLD chip selection.

This design uses Lattice's MachXO series of chips. This series of CPLDs integrates some of the functions of FPGAs. In addition to the built-in rich LUT resources, there are a large number of distributed SRAM bits and embedded SRAM blocks dedicated to FIFO design. The analog phase-locked loop (PLL) supports multiplication, division, etc. of the clock signal, and the I/O pins can be configured to be 1.2/1.5/1.8/3.3V level compatible.

3.2 Hardware programming based on Verilog HDL language

This design uses the Verilog HDL language for protocol chip programming. The Verilog HDL language is a hardware description language. When designing a digital chip, it can be described hierarchically and can be time series modeled. This design uses a hybrid design mode, the main design of the module is state machine, protocol frame detection, FIFO controller design.

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