ASIC design of SD/MMC card controller based on ARM9

0 Preface

Nowadays, the rapid development of multimedia digital products, among which the various audio and video functions continue to increase, so that the requirements of the system for the performance, capacity, security and other aspects of storage media are increasing. Both MMC cards and SD cards are flash-based storage devices. In recent years, they have become the standard in the flash memory market with high storage capacity, fast data transfer rate, and great mobility flexibility and higher security. Widely used in mobile phones, MP3, MP4, handheld computers and other products. It can be seen that it has become a common functional interface in SOC chips for portable digital electronic products.

The SD/MMC controller designed in this paper is based on a 3G mobile phone baseband chip. The core of the SD/MMC controller is ARM926EJ, the system bus architecture is AMBA, and the controller is connected to the APB bus. By analyzing the specifications of the SD card and the MMC card, the SD/MMC card controller IP core conforming to the specification is implemented by Verilog HDL. The IP is integrated and optimized under the SMIC 0.13um standard cell process library.

1 SD / MMC card controller works

SD (Secure Digital) cards and MMC (Multi Media Card) cards are two types of data storage cards that are common on the market. The SD card is backward compatible with the MMC card.

The basic characteristics of the two are the same, but there are some differences in the data interface and transmission mode: the SD card has 4 data lines, and the MMC card has only 1; the SD card supports security protection; and the MMC card supports bit stream transmission (not Limit transmission, that is, the transmission must be stopped when the stop command must be accepted).

The controller is to initialize, read, write and other operations on the SD/MMC card through the SD/MMC bus. The bus includes a clock line CLK, a command line CMD, a data line DAT3-DAT0 (the MMC card has only DAT0), and the like. After power-on, the controller must transmit commands to the card according to a certain bus protocol to initialize it. There are three data formats on the bus: command packets, response packets, and data packets. Since data and commands may be in error during transmission, the command has a 7-bit CRC and the data has a 16-bit CRC.

When the controller reads the card, it converts the received serial data (possibly a bit stream or multiple blocks) into parallel data and stores it in the FIFO. The write operation is also the same, the controller takes the parallel data out of the FIFO and sends it out serially.

The working clock of the SD/MMC card comes from the controller, and a series of operations such as command or data transmission to the card are synchronized with the clock. The clock can be configured by the controller to accommodate the different clock frequencies required for the card to function properly in different operating states. It should be noted that the maximum operating frequency of the SD card is 25Mhz, and the maximum operating frequency of the MMC card is 20Mhz.

In short, the controller not only needs to output the appropriate working clock, but also completes the normal operation of the command/response and data reading and writing, and performs CRC check on the command and data, and the interrupt is generated and cleared in time.

2 controller design and implementation

2.1 Module division

In the whole SOC, our TD baseband chip uses the ARM926EJ-S core, and the system architecture is AMBA bus. In the design, the SD/MMC card controller is suspended as the SLB of the APB on the APB bus, and the ARM accesses and controls the module through the APB bus. This module is mainly divided into three parts: interface module, CMD control module and DATA control module. Its structural block diagram is shown in Figure 1.

Figure 1 SD / MMC controller structure

The interface module is connected to the ARM APB bus. Through this module, the ARM can read and write the corresponding registers, thereby realizing the control of the module and the external memory card. Its read and write timing is based on the APB bus read and write timing, see the literature.

The CMD control module mainly sends and receives signals on the CMD line. The command length sent by the controller to the card is fixed at 48 bits, and the response length received from the card is not fixed, and there are short response (48 bits) and long response (136 bits).

Among them, the sub-module containing CRC7, whether it is a command or a response, uses a CRC check.

The DATA control module mainly receives data through the RXDATA data line and transmits data through TXDATA. There are two main data transmission methods: bit stream data transmission and multi-block data transmission. In addition, the controller also supports non-responsive packet data transmission. To ensure correct transmission, a submodule containing the CRC16 checksum is included.

2.2 Design of CMD Control Module

Since the operation commands of the SD/MMC card are inconsistent, the command is not decoded in the module, but the type of the command is set by software. The signal block data read command (CMD17), the write data command (CMD24), the multi-block data read data command (CMD18), the write data command (CMD25), etc. require the control module to be based on the contents of the SD_CMD_INDEX register. To issue the corresponding commands and make different state transitions. The state transition diagram of the CMD control module is shown in Figure 2.

Figure 2 State transition of the CMD control module

2.3 DATA control module design

The main function of this module is to send data to and read data from the card. In addition, for the SD card, the module can detect whether the card is inserted through DATA[3], send a read wait signal through DATA[2], and receive through DATA[1]. The interrupt signal sent by the card and the DATA[0] are used to detect whether the card is busy.

There are other functional modules on the APB bus, such as the SPI interface controller, CAMERA controller, etc. Since the bus cannot be occupied all the time, it is too late to process the data received or read the data, or it is too late to acquire new transmission data. So we take the data cache and add a 64bytes FIFO.

When the controller reads the card, it needs to send the CMD9 command to obtain the CSD register data of the card, including the data length of the card, the card storage capacity, and the maximum clock speed of the card. The controller can continue to read data until a stop transmission command is sent to the card; or a specified number of data blocks are read.

During the data reading process, if the card detects an error, such as out of range, address alignment error, etc., the card will stop data transmission, stop in the sending-data state, the controller needs to send a stop transmission command, at this time, the card will send an error message. Return to the controller via the response.

The controller can continue to write data to the card until a stop transmission command is sent to the card; or a specified number of data blocks are written. In the process of writing data, if the card detects an error, such as write protection, address out of range, address alignment error, etc., the card will stop receiving data, stop in the Receiving-data state, the controller needs to send a stop transmission command, then the card will The error message is returned to the controller via the response packet. After a data block is written, the card needs to write the data to the internal Flash for a period of time. The controller needs to check the status of the card, and the next command can be sent after the card has finished writing the data.

2.4 CRC algorithm design

The CRC check is used in both the CMD control module and the DATA control module. The CRC7 is used in the CMD control module, and its formula is G(x)=x7+x3+1. The logic diagram for implementing its algorithm is shown in Figure 3.

Figure 3 CRC7 generation logic

The CRC16 is used in the DATA control module, and its formula is G(x)=x16+x12+x5+1. The algorithm logic diagram is the same as the CRC7 class test, and we will not repeat them here.

The two checks are essentially the same, the latter being more accurate and adapting to the transmission verification of data, especially long data.

3 Functional verification and synthesis

Simulated using Mentor's ModelSim software, which is licensed for use on PC, Solaris, HP-UX or Linux platforms, and supports VHDL or Verilog Hardware Description Language (HDL) emulation. It supports behavioral level simulation and VHDL or Verilog simulation excitation for all devices.

In order to test the correctness of the design, the testbench module was written, which included a prototype of the SD card described by HDL (so that the controller can operate the card), including generating clock signals, outputting commands, reading and writing data, and generating Interrupted, etc. The following is an example of testing SDMMC read/write registers, sending command receive responses, and 4-block block data transfer.

After the chip select signal is satisfied, the APB bus first configures the internal register, then determines the transmission of the command, attaches the check code of CRC7, and finally receives the CRC7 check code of the response and response.

All transmission methods such as streaming, single block, and multi-block data are simulated, and they are integrated by the current industry's most popular comprehensive tool: SYNOPSYS's DesignCompiler. After setting the constraints of the script script, the timing and area of ​​the controller are optimized by DC, and the working frequency satisfies the baseband chip frequency of 125Mhz (up to 200 or more), and the area is 30,000 gates, which is more than the mainstream 40,000 gates. Reduced and saved area.

Finally, Xilinx's xc4vlx200-10ff1513 chip is used for FPGA verification. The test results show that the controller can transmit data to the mainstream SDMMC card on the market, which meets the requirements of the entire SOC.

4 Conclusion

After the verification, the above design was packaged and manufactured using SMIC's 0.13um process library, and the latest SD1.0 and MMC3.31 protocols were implemented and embedded in the ASIC, making the TD terminal externally extended. Storage, saving user overhead. Not only that, the controller can be ported to a variety of multimedia processing-based ASIC chips as a mature IP core, and its application is very extensive.

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